Semiconductor memory devices are employed to store data in a great variety of host systems. In some system systems, simultaneous data input/output (I/O) through multiple data access ports may be required.
One type of semiconductor memory device having two access ports is called a dual-port memory. Dual-port memories are commonly used in a number of fields, such as digital image processing to store data. In such applications, dual-port memories may be known as “video memory” and have a RAM port accessible via a random sequence and a Shared Memory Area (SAM) port accessible only via a serial sequence.
In contrast with such dual-port (or video) memories, regular dynamic random access memories (DRAM) do not include a SAM port associated with a shared memory area. Rather, DRAM comprises a memory cell array accessible via by different processors through a plurality of access ports. To distinguish this type of memory device from dual-port (or video) memories, they will hereafter be referred to as multiport memories or multipath accessible memories. One example of a conventional memory device having a shared memory area and being adapted for use in a multiprocessor system, (i.e., adapted for access by a plurality of processors) is disclosed in published U.S. Patent Application 2003/0093628. FIG. 1 is a block diagram of the multiprocessor system 50 described in the U.S. Patent Application 2003/0093628.
Referring to FIG. 1, an array of memory cells 35 includes first, second and third portions. First portion 33 of memory array 35 may be accessed by only a first processor 70 via a first port 37. Second portion 31 of memory array 35 may be accessed by only a second processor 80 via a second port 38, and third portion 32 may be accessed by either one of the first and second processors 70 and 80. The respective size of first and second portions 33 and 31 of memory array 35 is changeable depending on the operating load of first and second processors 70 and 80. Having this access architecture, memory array 35 is referred to as “a memory type or disk storage type” array.
To realize third portion 32 commonly accessed by first and second processors 70 and 80 within the memory array 35 using DRAM components and access techniques, a number of technical issues must be addressed. As a first issue, the layout of the respective memory areas within memory array 35 must be considered. Next, adequate read/write path control techniques associated with the respective access ports must be considered. Further, the inevitable pressure to expand third portion 32, as the overall data storage capacities of the memory array 35 are increased must be addressed.